Freescale Semiconductor /MKL24Z4 /UART0 /C4

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Interpret as C4

7 43 0 0 00 0 0 0 0 0 0 0 0OSR0 (0)M10 0 (0)MAEN2 0 (0)MAEN1

MAEN2=0, M10=0, MAEN1=0

Description

UART Control Register 4

Fields

OSR

Over Sampling Ratio

M10

10-bit Mode select

0 (0): Receiver and transmitter use 8-bit or 9-bit data characters.

1 (1): Receiver and transmitter use 10-bit data characters.

MAEN2

Match Address Mode Enable 2

0 (0): All data received is transferred to the data buffer if MAEN1 is cleared.

1 (1): All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.

MAEN1

Match Address Mode Enable 1

0 (0): All data received is transferred to the data buffer if MAEN2 is cleared.

1 (1): All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.

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